Embodiments of the present invention relate to the field of junction field effect transistors (JFETs). In particular, embodiments of the present invention relate to gate drive circuits for JFETs.
Junction field effect transistors (JFETs) are majority carrier devices that conduct current through a channel that is controlled by the application of a voltage to a p-n junction. JFETs may be constructed as p-channel or n-channel and may be operated as enhancement mode devices or depletion mode devices.
The most common JFET type is the depletion mode type. The depletion mode device is a xe2x80x9cnormally onxe2x80x9d device that is turned off by reverse biasing the p-n junction so that pinch-off occurs in the conduction channel. P-channel depletion mode devices are turned off by the application of a positive voltage between the gate and source (positive Vgs), whereas n-channel depletion mode devices are turned off by the application of a negative voltage between the gate and source (negative Vgs). Since the junction of a depletion mode JFET is reverse biased in normal operation, the input voltage Vgs, can be relatively high. However, the supply voltage between the drain and source (Vds) is usually relatively low.
Prior Art FIG. 1A shows a general schematic for an n-channel depletion mode JFET with Vgs=Vds=0. The JFET has two opposed gate regions 10, a drain 11 and source 12. The drain 11 and source 12 are located in the n-doped region of the device and the gates 10 are p-doped. Two p-n junctions are present in the device, each having an associated depletion region 13. A conductive channel region 14 is shown between the two depletion regions 13 associated with the p-n junctions.
In operation, the voltage variable width of the depletion regions 13 is used to control the effective cross-sectional area the of conductive channel region 14. The application of a voltage Vgs between the gates 10 and source 12 will cause the conductive channel region to vary in width, thereby controlling the resistance between the drain 11 and the source 12. A reverse bias, (e.g., a negative Vgs), will cause the depletion regions to expand, and at a sufficiently negative value cause the conductive channel to xe2x80x9cpinch offxe2x80x9d, thereby turning off the device.
The width of the depletion regions 13 and the conductive channel region 14 are determined by the width of the n-doped region and the dopant levels in the n-doped and p-doped regions. If the device shown in FIG. 1A were constructed with a narrow n-doped region, such that the two depletion regions merged into a single continuous depletion region and the conductive channel region 14 had zero width, the result would be the device shown in FIG. 1B.
Enhancement mode, or xe2x80x9cnormally offxe2x80x9d JFETs are characterized by a channel that is sufficiently narrow such that a depletion region at zero applied voltage extends across the entire width of the channel. Application of a forward bias reduces the width of the depletion region in the channel, thereby creating a conduction path in the channel. P-channel enhancement mode JFETs are turned on by the application of a negative Vgs, and n-channel enhancement mode JFETs are turned on by the application of a positive Vgs. The input voltage of an enhancement mode JFET is limited by the forward voltage of the p-n junction.
Prior Art FIG. 1B shows a general schematic of an n-channel enhancement mode JFET with Vgs=Vds=0. The enhancement mode device is xe2x80x9cnormally offxe2x80x9d since the conductive channel width is zero due to the extent of the two depletion regions 13B. The application of a sufficient forward bias (e.g. positive Vgs) to the device of FIG. 1B will cause the depletion regions 13B to contract, thereby opening a conductive channel.
Although the depletion mode and enhancement mode devices shown schematically in FIG. 1A and FIG. 1B are n-channel devices, depletion mode and enhancement mode devices could be constructed with a reversed doping scheme to provide p-channel devices.
Historically, metal-oxide semiconductor field effect transistors (MOSFETs) have been much more widely used than JFETs; and among JFETs, the depletion mode device has been more widely used than the enhancement mode device. However, the adoption of submicron processes for device fabrication and the resulting higher speeds, lower voltages, and greater current demands in integrated circuits has created new opportunities for the application of JFETs in power conditioning circuits such as buck converters and switching power supplies.
switching mode regulators are preferred to linear devices due to their greater efficiency. This increased efficiency is achieved by operating the switch (transistor) so that it is either fully on or fully off. Circuits used to drive a transistor for a switching application are designed with the goal of providing a fast transition between the xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states of the transistor switch.
JFETs are capable of being driven by low voltages while maintaining excellent breakdown characteristics when compared to MOSFETs. Since there is no insulator associated with gate/drain and gate/source interfaces of a JFET (only a p-n junction), forward bias results in conduction at voltages that are very low compared to the reverse bias that the device is capable of withstanding. JFETs also have a much greater resistance to damage from electrostatic discharge (ESD) than MOSFETs.
As a result of the widespread use of MOSFET devices, driver circuits and circuit designs for MOSFETs are readily available with a relatively low cost. However, due to the fundamental differences between MOSFETs and JFETs, these conventional MOSFET drivers are not well suited for driving JFETs.
Accordingly, a matching circuit for coupling a conventional metal-oxide semiconductor field effect transistor (MOSFET) driver to the gate of an enhancement mode junction field effect transistor (JFET)is described herein. A driver circuit optimized for driving a MOSFET is combined with a matching circuit to provide gate drive for a JFET.
More specifically, in an embodiment of the present invention, a matching circuit comprising a capacitor and a resistor in parallel is used to couple the output of a conventional MOSFET driver to the gate of an enhancement mode JFET.
In another embodiment of the present invention, particular values of resistance and capacitance are used in matching a conventional MOSFET driver to a JFET with a gate grid array structure. For driving enhancement mode JFETs having a gate grid array structure, the range of resistor values may be from 10 to 200 ohms, and the range of capacitor values may be from 1 to 100 nF, in one example. For devices having a low pinch-off voltage (e.g., a pinch-off voltage less than 0.4 volts), a preferred range of resistor values is 100 to 2000 ohms.
In a further embodiment, a diode or a plurality of diodes is coupled in series with the resistor of the matching circuit described above, in order to provide a gate bias for the JFET.
The present invention has the advantage of enabling common MOSFET drivers to be used to be used as enhancement mode JFET drivers. The invention also has the advantage of simplifying drive requirements in circuits having both JFETs and MOSFETs, by using a common driver for both transistor types.